Information about 1t Sram

Computer memory types

Volatile DRAM eDRAM SRAM 1T-SRAM Upcoming Z-RAM TTRAM Historical Williams tube Delay line memory Selectron tube

Non-Volatile ROM PROM EAROM EPROM EEPROM Flash memory Upcoming FeRAM MRAM PRAM SONOS RRAM NRAM Historical Drum memory Magnetic core memory Bubble memory

1T-SRAM is MoSys's implementation of embedded DRAM on a conventional digital-logic (standard-cell) ASIC process.

Conventional DRAM devices (ICs) are designed and built for heavily DRAM-optimized processes to maximize bit density, rendering traditional DRAM cell designs incompatible with nearly all commercial digital-logic CMOS foundry processes. Embedded DRAM is essentially the same RAM-cell ported to a more logic-optimized CMOS foundry process, allowing a designer to pair a digital-logic circuit with a sizable quantity of embedded RAM.

Although the basic storage cells require refresh like any other DRAM, they are coupled with a controller that hides all DRAM-specific operations such as precharging and refresh, and thus may be used just like SRAM.

In development since the early 1990s, MoSys's 1T-SRAM combines the ease of use of SRAM with the high bit-density and lower-power consumption of embedded DRAM. MoSyS markets 1T-SRAM as physical IP for embedded (on-die) use in System-on-a-chip (SOC) applications. It is available on a variety of foundry processes, including (but not limited to) NEC, TSMC, and UMC. Many engineers use the terms 1T-SRAM and "embedded DRAM" interchangeably, as some foundry processes only provide Mosys's offering in lieu of e-DRAM. However, other foundries list the two as clearly distinct offerings.

Technology

1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 Kibit in total) coupled to a bank-sized SRAM cache and an intelligent controller. Although space-inefficient compared to regular DRAM, the short word lines allow much higher speeds, so the array can do a full sense and precharge (RAS cycle) per access, providing high-speed random access. Each access is to one bank, allowing unused banks to be refreshed at the same time. Additionally, each row read out of the active bank is copied to the bank-sized SRAM cache. In the event of repeated accesses to one bank, which would not allow time for refresh cycles, there are two options: either the accesses are all to different rows, in which case all rows will be refreshed automatically, or some rows are accessed repeatedly. In the latter case, the cache provides the data and allows time for an unused row of the active bank to be refreshed.

There have been four generations of 1T-SRAM:

Original 1T-SRAM

About half the size of 6T-SRAM, less than half the power. ; 1T-SRAM-M : Variant with lower standby power consumption, for applications such as cell phones. ; 1T-SRAM-R : Incorporates ECC for lower soft error rates. To avoid an area penalty, it uses smaller bit cells, which have an inherently higher error rate, but the ECC more than makes up for that. ; 1T-SRAM-Q : This "quad-density" version uses a slightly non-standard fabrication process to produce a smaller folded capacitor, allowing the memory size to be halved again over 1T-SRAM-R. This does add slightly to wafer production costs, but does not interfere with logic transistor fabrication the way conventional DRAM capacitor construction does.

Comparison with other embedded memory technologies

Although not nearly as fast as 6-transistor SRAM, 1T-SRAM requires half to a quarter the space and less than half the power.

1T-SRAM boasts faster speed than e-DRAM, and the "quad-density" variant is only slightly larger (10–15% is claimed). On most foundry processes, designs with e-DRAM require additional (and costly) masks and processing steps, offsetting the cost of a larger 1T-SRAM die. Also, some of those steps require very high temperatures and must take place after the logic transistors are formed, possibly damaging them.

1T-SRAM is also available in device (IC) form. The Nintendo GameCube was the first video game system to use 1T-SRAM as a primary (main) memory storage; the GameCube possesses several dedicated 1T-SRAM devices. 1T-SRAM is also used in the successor to the GameCube, Nintendo's Wii console.

For extremely large (>1MB) on-chip RAM, e-DRAM is generally preferred. For high-speed applications, SRAM remains dominant. 1T-SRAM fits in between, overlapping mostly with e-DRAM.

Note that this is not the same as 1T DRAM, which is a "capacitorless" DRAM cell built using the parasitic channel capacitor of SOI transistors rather than a discrete capacitor.[1]

MoSys claims the following sizes for 1T-SRAM arrays:

1T-SRAM Cell sizes (μm²/bit or mm²/Mbit)

	0.25 μm	0.18 μm	0.13 μm	90 nm	65 nm	45 nm
6T-SRAM bit cell	7.56	4.65	2.43	1.36	0.71	0.34
6T-SRAM with overhead	11.28	7.18	3.73	2.09	1.09	0.52
1T-SRAM bit cell	3.51	1.97	1.10	0.61	0.32	0.15
1T-SRAM with overhead	7.0	3.6	1.9	1.1	0.57	0.28
1T-SRAM-Q bit cell			0.50	0.28	0.15	0.07
1T-SRAM-Q with overhead			1.05	0.55	0.29	0.14

References

• Peter N. Glaskowsky (1999-09-13). "MoSys Explains 1T-SRAM Technology". Microprocessor Report 13. Retrieved on 2007-10-06. 
• Jones, Mark-Eric (2003-10-14). "1T-SRAM-Q™: Quad-Density Technology Reins in Spiraling Memory Requirements". MoSys, Inc.. Retrieved on 2007-10-06.[ ]
• MoSys homepage
• US Patent 6,256,248 shows the DRAM array at the heart of 1T-SRAM.
• US Patent 6,487,135 uses the term "1T DRAM" to describe the innards of 1T-SRAM.
• Ismini Scouras. "1-T SRAM macros are preconfigured for fast integration in SoC designs", eeProductCenter, 2005-06-15. Retrieved on 2007-10-06. 
• Anthony Cataldo. "NEC, Mosys push bounds of embedded DRAM", EE Times, 2002-12-16. ISSN 0192-1541. Retrieved on 2007-10-06. 

See also

US Patent 7,146,454 "Hiding refresh in 1T-SRAM Architecture"* (by Cypress Semiconductor describes a similar system for hiding DRAM refresh using an SRAM cache.